This invention relates generally to plasma etching during integrated circuit fabrication, and more particularly to methods and apparatus for preventing undesirable plasma formation during such fabrication.
Integrated circuits are commonly fabricated on and within a surface region of a semiconductor substrate, such as a wafer of silicon. During such fabrication, various layers are produced within the substrate or deposited thereon. Some of these layers are then sized and dimensioned to form desired geometric patterns by means of various etching techniques. Such etching techniques include xe2x80x9cwetxe2x80x9d etching techniques, which typically use one or more chemical reagents brought into direct contact with the substrate, or xe2x80x9cdryxe2x80x9d etching techniques, such as plasma etching.
Numerous plasma-based etching techniques are known in the art, including what is commonly called the plasma etching mode, as well as reactive ion etching and reactive ion beam etching. In any of the wide variety of plasma etching techniques, a plasma is created by introducing a gas into a chamber in which one or more electrodes (commonly driven by an RF generator) generate the plasma by disassociation of the gas molecules into various ions, free radicals and electrons. The plasma then reacts with the material being etched from the semiconductor substrate.
FIG. 1 depicts a prior art plasma etching device 10, such as the Lam 9100, manufactured by Lain Research, Inc. The plasma etching device 10 includes an electrode such as a planar coil electrode 12, which is positioned proximate to a plate or window 14 formed from a suitable dielectric material. The window 14 is spaced apart from a dielectric gas distribution plate 16, with the space sealed by an O-ring 18. Source gases from which the plasma is to be generated are inserted into the gap formed between the window 14 and gas distribution plate 16. The source gases then diffuse through a plurality of openings or holes 20 included in the gas distribution plate 16 into a reaction chamber 22xe2x80x94the wall of which is typically grounded.
A high-voltage RF signal is applied to the planar coil electrode 12 and ignites a plasma within the reaction chamber 22. Ignition of the plasma occurs primarily by capacitive coupling of the electrode 12 with the source gas, due to the large magnitude voltages applied to the electrode. Once ignited, the plasma is sustained by electromagnetic induction effects associated with a time-varying magnetic field caused by the RF signal applied to the electrode 12.
A semiconductor wafer 24 is positioned within the reaction chamber 22 and is supported by a wafer platform or chuck 26. The chuck 26 is typically electrically biased to provide ion energies impacting the wafer 24 which are approximately independent of the RF voltage applied to the electrode 12. Volatile reaction products, as well as plasma species which did not interact with the wafer 24, are then pumped out of the reaction chamber 22, usually by means of a vacuum pump.
One disadvantage of devices such as the plasma etching device 10 of FIG. 1 is the existence of xe2x80x9chole lightupxe2x80x9d effects. The capacitive coupling of the electrode 12 with the gases and/or plasma in the reaction chamber 22 can create electric fields of sufficient strength to ignite plasmas in or near the holes 20 of the gas distribution plate 16. This causes a number of problems. For example, when etching dielectric layers on the semiconductor wafer 24, source gases such as fluorocarbons are used, and the hole lightup effects cause polymer deposition in or near the holes 20 and on the window 14. In the case of particle deposition in or near the holes 20, the distribution of source gases into the reaction chamber 22 can be changed, resulting in (among other things) a potential lack of uniformity in the etching process occurring within the chamber. Those polymers or other materials deposited on the window 14 may ultimately flake off, resulting in particle contamination within the reaction chamber 22. Additionally, energy that was intended to ignite plasma within the reaction chamber 22 is instead wasted in the plasma ignition associated with hole lightup.
To avoid hole lightup effects, the current approach includes careful positioning, configuring, and sizing of the holes 20 included in the gas distribution plate 16. The holes 20 not positioned directly below portions of the planar coil electrode 12 suffer from lesser hole lightup effects than those holes positioned approximately below the electrode. As such, careful alignment and positioning of the holes 20 relative to the electrode 12 is required. Even so, some hole lightup effects still occur, resulting in deposition of particles and wear on portions of the holes 20. The gas distribution plate is not, however, readily moved or rotated to distribute these effects, because such movement is difficult to implement within the alignment constraints. Therefore, hole lightup effects and the constraints caused by minimizing such effects result in lower useful lifetimes for plasma etching device components such as the gas distribution plate 16. Furthermore, the location and configuration of the holes 20 cannot be designed for optimal process performance, due to the design constraints imposed by hole lightup effects.
In accordance with an embodiment of the present invention a plasma etching device for etching selected materials during integrated circuit fabrication is provided. The plasma etching device includes a reaction chamber adapted to receive the selected materials. The plasma etching device also includes gas flow structure adjoining the reaction chamber and including an opening through which gas can flow into the reaction chamber. An electrode is operable to produce an electromagnetic field for application to the gas within the reaction chamber to ignite a plasma therewithin. A shield structure is provided which is operable and positioned to suppress the electromagnetic field in a location proximate to and within the opening to prevent plasma formation therewithin.